Aparna V S

Hi,

I am Aparna V S, recently completed my internship at Scihub Semiconductor Solutions Pvt. Ltd. (SCIHUBSS), and prior to that I worked as a Trainee at Bitsilica. I hold an M.Tech in VLSI Design and have gained practical experience through my academic projects and professional training and have hands-on experience in RTL design, ASIC design flow, simulation, and verification.

During my internship at Scihub Semiconductor Solutions and my role as an RTL Design Trainee at Bitsilica, I worked with Verilog HDL, Xilinx Vivado, and QuestaSim/ModelSim. My work involved RTL development, functional simulation, and testbench development, giving me a strong understanding of the RTL-to-implementation flow. I have also completed projects involving SPI-based digital design and JTAG controller implementation, strengthening my knowledge of digital design and verification.

With a strong technical foundation, excellent problem-solving skills, and the ability to collaborate effectively with cross-functional teams, I am confident in my ability to quickly learn and contribute to your team.

I am currently looking for opportunities and would be truly grateful if you could kindly consider my profile for any suitable openings now or in the future within your organization. It would mean a lot to me and would be greatly helpful for my career growth.

Thank you for your time and consideration. I look forward to the opportunity to discuss how I can contribute to your organization.

Warm regards,

Aparna V S